( en | de | ru )

 

Disambiguation of "Ashouei, Maryam"

Author of the publication

copydeleteadd this publication to your clipboard
Energy Efficiency Using Loop Buffer based Instruction Memory Organizations.

, , , , , , and . IWIA, page 59-67. IEEE, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Maryam Naderian

Maryam Fakhury

Maryam Khodaverdi

Maryam Balke

Maryam Ramezani

 

Other publications of authors with the same name

Human++: Key Challenges and Trade-offs in Embedded System Design for Personal Health Care., , , , , , and . DSD, page 4-10. IEEE Computer Society, (2011)8T SRAM with Mimicked Negative Bit-lines and Charge Limited Sequential sense amplifier for wireless sensor nodes., , , , , and . ESSCIRC, page 531-534. IEEE, (2011)Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums., , and . IOLTS, page 173-182. IEEE Computer Society, (2007)Variability aware cell library optimization for reliable sub-threshold operation., and . ESSCIRC, page 42-45. IEEE, (2012)Extending Synchronization from Super-Threshold to Sub-threshold Region., , , , and . ASYNC, page 85-93. IEEE Computer Society, (2010)Probabilistic Error Correction in Linear Digital Filters Using Checksum Codes., , and . LATW, page 192-197. IEEE, (2006)Noise Margin Based Library Optimization Considering Variability in Sub-threshold., , and . PATMOS, volume 7606 of Lecture Notes in Computer Science, page 72-82. Springer, (2012)Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS., , and . VLSI Design, page 27-32. IEEE Computer Society, (2008)Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM., , , , , and . DATE, page 1042-1047. IEEE, (2012)Approximate compressed sensing: ultra-low power biosignal processing via aggressive voltage scaling on a hybrid memory multi-core processor., , , , , , , and . ISLPED, page 45-50. ACM, (2014)