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On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process., и . ISCAS (5), стр. 529-532. IEEE, (2002)ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure., и . ISCAS (2), стр. 1182-1185. IEEE, (2005)Improvement on ESD Robustness of Lateral DMOS in High-voltage CMOS ICs by Body Current Injection., , , , и . ISCAS, стр. 385-388. IEEE, (2009)Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-µm CMOS technology., и . ISCAS (2), стр. 577-580. IEEE, (2004)A new Schmitt trigger circuit in a 0.13 µm 1/2.5 V CMOS process to receive 3.3 V input signals., и . ISCAS (2), стр. 573-576. IEEE, (2004)Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology., и . IEEE J. Solid State Circuits, 44 (3): 956-964 (2009)Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification., , , , , , , , , и 2 other автор(ы). IEEE J. Solid State Circuits, 56 (10): 3062-3076 (2021)The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs., и . IEEE J. Solid State Circuits, 40 (8): 1751-1759 (2005)A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18- μm 1.8-V/3.3-V Low-Voltage CMOS Process., , , и . IEEE Trans. Biomed. Circuits Syst., 11 (5): 1087-1096 (2017)Implantable Stimulator for Epileptic Seizure Suppression With Loading Impedance Adaptability., , и . IEEE Trans. Biomed. Circuits Syst., 7 (2): 196-203 (2013)