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A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS.

, , , , , , , and . CICC, page 1-4. IEEE, (2017)

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3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS., , , , , , and . ISSCC, page 1-3. IEEE, (2015)Origin of Hysteresis in CH3NH3PbI3 Perovskite Thin Films, , , , , , , , and . Advanced Functional Materials, 27 (37): n/a--n/a (2017)A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS., , , , and . CICC, page 1-4. IEEE, (2018)A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS., , , , , , , and . CICC, page 1-4. IEEE, (2017)A 10MHz 2mA-800mA 0.5V-1.5V 90% peak efficiency time-based buck converter with seamless transition between PWM/PFM modes., , , and . CICC, page 1-4. IEEE, (2017)A three-data differential signaling over four conductors with pre-emphasis and equalization: a CMOS current mode implementation., , and . IEEE J. Solid State Circuits, 41 (3): 633-641 (2006)Design of Energy-Efficient Cryptographically Secure Pseudo-Random Number Generators Using High-Level Synthesis., and . ISOCC, page 351-352. IEEE, (2023)Automated generation of product use case scenarios in product line development., , , and . CIT, page 760-765. IEEE Computer Society, (2008)1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture., , , , , , , , , and 5 other author(s). ISSCC, page 128-129. IEEE, (2009)0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link., , , , , and . VLSI Technology and Circuits, page 30-31. IEEE, (2022)