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Design and performance of networks for super-, cluster-, and grid-computing: Part II.

, , and . J. Parallel Distributed Comput., 65 (11): 1301-1304 (2005)

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Power-efficient partially-adaptive routing in on-chip mesh networks., , and . ISOCC, page 65-66. IEEE, (2016)Design for scalability in enterprise SSDs., , and . PACT, page 417-430. ACM, (2014)An Analytic Model for Communication Latency in Wormhole-Switched k-ary n-Cube Interconnection Networks with Digit-Reversal Traffic., , and . ISHPC, volume 1940 of Lecture Notes in Computer Science, page 218-229. Springer, (2000)A Parallel Algorithm for Lagrange Interpolation on k-ary n-Cubes., , and . ACPC, volume 1557 of Lecture Notes in Computer Science, page 85-95. Springer, (1999)Chapter Six - Topology Specialization for Networks-on-Chip in the Dark Silicon Era., and . Advances in Computers, (2018)Chapter One - Dark Silicon and the History of Computing., and . Advances in Computers, (2018)Traffic-aware buffer reconfiguration in on-chip networks., and . VLSI-SoC, page 201-206. IEEE, (2015)Communication delay in hypercubes in the presence of bit-reversal traffic., , and . Parallel Comput., 27 (13): 1801-1816 (2001)Power- and performance-efficient cluster-based network-on-chip with reconfigurable topology., , and . Microprocess. Microsystems, (2016)Chapter One - Introduction to non-volatile memory technologies., and . Advances in Computers, (2020)