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Disambiguation of "Yesil, Serif"

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FPGA implementation of a fault-tolerant application-specific NoC design.

, , and . DTIS, page 1-6. IEEE, (2016)

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Manuela Yesil

Tacha Serif

Tanju Yesilkaya

Baris Serifsoy

Nursel Yesilkus

 

Other publications of authors with the same name

Efficient parallel implementation of the multiplicative weight update method for graph-based linear programs., , , , and . CoRR, (2023)Hardware Accelerator Design for Data Centers., , , , , and . ICCAD, page 770-775. IEEE, (2015)V-Combiner: speeding-up iterative graph processing on a shared-memory platform with vertex merging., , , , , and . ICS, page 9:1-9:13. ACM, (2020)Scheduling for heterogeneous systems in accelerator-rich environments., and . J. Supercomput., 78 (1): 200-221 (2022)Energy Efficient Architecture for Graph Analytics Accelerators., , , , , , and . ISCA, page 166-177. IEEE Computer Society, (2016)Speeding up SpMV for power-law graph analytics by enhancing locality & vectorization., , , and . SC, page 86. IEEE/ACM, (2020)A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (2): 420-430 (2018)Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications., , , , , and . ICCAD, page 676-681. IEEE, (2015)SPADE: A Flexible and Scalable Accelerator for SpMM and SDDMM., , , , , and . ISCA, page 19:1-19:15. ACM, (2023)Snug: architectural support for relaxed concurrent priority queueing in chip multiprocessors., , , , and . ICS, page 18:1-18:13. ACM, (2020)