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Disambiguation of "Sinha, Ashutosh"

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A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology.

, , , , , , , , , , , , , , , , , , and . ISSCC, page 108-109. IEEE, (2023)

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Prashant Sinha

Intermediate states in bivalent ion induced shrinking of polyacrylate coils on surfaces and in solution. TU Dresden, (2009)

Ashutosh Banerjee

Ashutosh Trivedi

Ashutosh Malaviya

Ashutosh Modi

 

Other publications of authors with the same name

A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 59 (1): 8-18 (January 2024)A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 49 (12): 3091-3103 (2014)A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS., , , , , , , , , and 15 other author(s). ISSCC, page 348-350. IEEE, (2011)A 1.0625 ~ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS., , , , , , , , , and 15 other author(s). IEEE J. Solid State Circuits, 46 (12): 3126-3139 (2011)2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS., , , , , , , , , and 13 other author(s). ISSCC, page 38-39. IEEE, (2014)A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology., , , , , , , , , and 9 other author(s). ISSCC, page 108-109. IEEE, (2023)CookieArmor : Safeguarding against cross-site request forgery and session hijacking., and . Secur. Priv., (2019)