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Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies.

, , , , , , , , , , , , , , и . ISSCC, стр. 528-529. IEEE, (2008)

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Sabine Soens

Charlotte Möser

Essays on monetary policy: a Bayesian approach. HU Berlin, (2009)

Charlotte Rau

Charlotte Donner

Charlotte Selge

 

Другие публикации лиц с тем же именем

Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS., , , , и . IEEE J. Solid State Circuits, 43 (11): 2422-2433 (2008)Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies., , , , , , , , , и 5 other автор(ы). ISSCC, стр. 528-529. IEEE, (2008)A CMOS 100 MHz to 6 GHz software defined radio analog front-end with integrated pre-power amplifier., , , , , , , , и . ESSCIRC, стр. 436-439. IEEE, (2007)A 60-GHz 8-Way Phased-Array Front-End With T/R Switching and Calibration-Free Beamsteering in 28-nm CMOS., , , , , , , и . IEEE J. Solid State Circuits, 53 (7): 2001-2011 (2018)A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication., , , , , , , , , и 4 other автор(ы). ISSCC, стр. 236-237. IEEE, (2013)Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance., , , и . DATE, стр. 270-275. IEEE Computer Society, (2005)A low-power 57-to-66GHz transceiver in 40nm LP CMOS with -17dB EVM at 7Gb/s., , , , , , , , , и 2 other автор(ы). ISSCC, стр. 268-270. IEEE, (2012)A 60GHz 8-way phased array front-end with TR switching and calibration-free beamsteering in 28nm CMOS., , , , , , и . ESSCIRC, стр. 203-206. IEEE, (2017)Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance, , , и . CoRR, (2007)Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's., , , , и . DATE, стр. 1520-1525. EDA Consortium, San Jose, CA, USA, (2007)