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Disambiguation of "Raveendran, Biju K."

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CAMP: a hierarchical cache architecture for multi-core mixed criticality processors.

, , , , , and . Int. J. Parallel Emergent Distributed Syst., 39 (3): 317-352 (May 2024)

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Biju John

Biju Mathew

Aman K K Bhasin

Biju Jose Thanka Nadar

K Schweizerhof

 

Other publications of authors with the same name

EFFS: Efficient Flash File System for Wireless Sensor Nodes., , , and . ESA, page 159-168. CSREA Press, (2007)MOESIF: a MC/MP cache coherence protocol with improved bandwidth utilisation., , and . Int. J. Embed. Syst., 11 (4): 493-507 (2019)Simulation based Performance Study of Cache Coherence Protocols., , and . iNIS, page 125-130. IEEE, (2015)Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors., , and . VLSID, page 65-70. IEEE Computer Society, (2015)Variants of Priority Scheduling Algorithms for Reducing Context-Switches in Real-Time Systems., , , and . ICDCN, volume 4308 of Lecture Notes in Computer Science, page 466-478. Springer, (2006)SACRED: Software Approach for Collaboration and Research Dissemination., , , and . Int. J. e Collab., 19 (1): 1-20 (2023)LAMCS: A leakage aware DVFS based mixed task set scheduler for multi-core processors., , and . Sustain. Comput. Informatics Syst., (2017)DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems., , and . VLSID, page 207-212. IEEE Computer Society, (2017)SMILEY: A Mixed-Criticality Real-Time Task Scheduler for Multicore Systems., , and . DS-RT, page 55-62. IEEE Computer Society, (2018)eduCloud: a VM communication aware, migration efficient cloud for scientific computing., , and . Int. J. Commun. Networks Distributed Syst., 18 (3/4): 329-352 (2017)