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Glitch-aware output switching activity from word-level statistics., , , and . ISCAS, page 1792-1795. IEEE, (2008)Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction., , and . FPT, page 105-112. IEEE, (2007)Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices., , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (6): 733-744 (2008)Exploration of heterogeneous reconfigurable architectures (abstract only)., , and . FPGA, page 268. ACM, (2005)Optimizing Floating Point Units in Hybrid FPGAs., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (7): 1295-1303 (2012)A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design., , and . FCCM, page 275-276. IEEE Computer Society, (2006)Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods., , , and . ACM Trans. Reconfigurable Technol. Syst., 4 (1): 3:1-3:23 (2010)Optimizing coarse-grained units in floating point hybrid FPGA., , , , and . FPT, page 57-64. IEEE, (2008)Exploration of Heterogeneous Reconfigurable Architectures.. FPL, page 719-720. IEEE, (2005)A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design., , and . FPL, page 1-6. IEEE, (2006)