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A 12-bit CMOS Current Steering D/A Converter for Embedded Systems., , , , , и . APCCAS, стр. 1671-1674. IEEE, (2006)An embedded 12-bit 80MS/s A/D/A interface for power-line communications in 0.13µm pure digital CMOS technology., , , , , , и . ISCAS (5), стр. 4626-4629. IEEE, (2005)Behavioral modeling of pipeline ADC building blocks., , и . I. J. Circuit Theory and Applications, 40 (6): 571-594 (2012)Electrical-level synthesis of pipeline ADCs., , и . APCCAS, стр. 1628-1631. IEEE, (2008)Design procedure for optimizing the power consumption of two-stage Miller compensated amplifiers in SC circuits., , и . ECCTD, стр. 452-455. IEEE, (2007)A power efficient neural spike recording channel with data bandwidth reduction., , , , и . ISCAS, стр. 1704-1707. IEEE, (2011)An optimization-based tool for the high-level synthesis of discrete-time and continuous-time ΣΔ modulators in the Matlab/Simulink environment., , , , , , и . ISCAS (5), стр. 97-100. IEEE, (2004)A Low-Power Programmable Neural Spike Detection Channel With Embedded Calibration and Data Compression., , , и . IEEE Trans. Biomed. Circuits Syst., 6 (2): 87-100 (2012)A 5.3mW, 2.4GHz ESD protected Low-Noise Amplifier in a 0.13μm RFCMOS technology., , , и . ECCTD, стр. 72-75. IEEE, (2007)Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits., , и . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (6): 1077-1087 (2009)