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Disambiguation of "Ruiz-Amaya, Jesús"

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A power efficient neural spike recording channel with data bandwidth reduction.

, , , , and . ISCAS, page 1704-1707. IEEE, (2011)

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Pedro Miguel d' Jesús Montilva

Jesús Araiza

Jesús Arambarri

Jesús Odriozola

Jesús Valle

 

Other publications of authors with the same name

A 12-bit CMOS Current Steering D/A Converter for Embedded Systems., , , , , and . APCCAS, page 1671-1674. IEEE, (2006)An embedded 12-bit 80MS/s A/D/A interface for power-line communications in 0.13µm pure digital CMOS technology., , , , , , and . ISCAS (5), page 4626-4629. IEEE, (2005)Electrical-level synthesis of pipeline ADCs., , and . APCCAS, page 1628-1631. IEEE, (2008)Behavioral modeling of pipeline ADC building blocks., , and . I. J. Circuit Theory and Applications, 40 (6): 571-594 (2012)Design procedure for optimizing the power consumption of two-stage Miller compensated amplifiers in SC circuits., , and . ECCTD, page 452-455. IEEE, (2007)An optimization-based tool for the high-level synthesis of discrete-time and continuous-time ΣΔ modulators in the Matlab/Simulink environment., , , , , , and . ISCAS (5), page 97-100. IEEE, (2004)A power efficient neural spike recording channel with data bandwidth reduction., , , , and . ISCAS, page 1704-1707. IEEE, (2011)A Low-Power Programmable Neural Spike Detection Channel With Embedded Calibration and Data Compression., , , and . IEEE Trans. Biomed. Circuits Syst., 6 (2): 87-100 (2012)A 5.3mW, 2.4GHz ESD protected Low-Noise Amplifier in a 0.13μm RFCMOS technology., , , and . ECCTD, page 72-75. IEEE, (2007)Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (12): 2816-2828 (2011)