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On the fault coverage of gate delay fault detecting tests., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (1): 78-94 (1997)On the computation of the ranges of detected delay fault sizes., and . ICCAD, page 126-129. IEEE Computer Society, (1989)Distributed Solutions to the Delay Fault Test Quality Evaluation Problem., and . HPDC, page 177-185. IEEE, (1994)Parallel Delay Fault Coverage and Test Quality Evaluation., and . ITC, page 113-122. IEEE Computer Society, (1995)Parallel, multi-DUT testing in an open architecture test system., , and . ITC, page 9. IEEE Computer Society, (2005)On Multiple Path Propagating Tests for Path Delay Faults., and . ITC, page 393-402. IEEE Computer Society, (1991)On the design of path delay fault testable combinational circuits., and . FTCS, page 374-381. IEEE Computer Society, (1990)Efficient multiple path propagating tests for delay faults., and . J. Electron. Test., 7 (3): 157-172 (1995)On Unified Delay Fault Testing., and . VLSI Design, page 265-268. IEEE Computer Society, (1993)Design of Scan-Based Path-Delay-Testable Sequential Circuits., and . ITC, page 962-971. IEEE Computer Society, (1993)