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Fast and flexible buffer trees that navigate the physical layout environment.

, , , and . DAC, page 24-29. ACM, (2004)

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Fast and flexible buffer trees that navigate the physical layout environment., , , and . DAC, page 24-29. ACM, (2004)Buffered Steiner trees for difficult instances., , , , , , , , , and . ISPD, page 4-9. ACM, (2001)Porosity aware buffered steiner tree construction., , , , and . ISPD, page 158-165. ACM, (2003)Techniques for improved placement-coupled logic replication., , and . ACM Great Lakes Symposium on VLSI, page 211-216. ACM, (2006)Porosity-aware buffered Steiner tree construction., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (4): 517-526 (2004)Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique., , , , , , and . ISPD, page 104-109. ACM, (2002)Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages., and . ISPD, page 98-103. ACM, (2002)A fast algorithm for identifying good buffer insertion candidate locations., , and . ISPD, page 47-52. ACM, (2004)An approach to placement-coupled logic replication., , and . DAC, page 711-716. ACM, (2004)S-Tree: a technique for buffered routing tree synthesis., and . DAC, page 578-583. ACM, (2002)