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Disambiguation of "Dasalukunte, Deepak"

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A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference.

, , , , , , , and . VLSI Technology and Circuits, page 36-37. IEEE, (2022)

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Deepak Bararia

Deepak Ajwani

Deepak Jain

Deepak Samuel

Deepak Mathaikutty

 

Other publications of authors with the same name

A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference., , , , , , , and . VLSI Technology and Circuits, page 36-37. IEEE, (2022)Low latency communication over commercially available LTE and remote driving., , , , and . CoRR, (2022)An Ultra-Low Power, Fully Integrated Wake-Up Receiver and Digital Baseband with All-Digital Impairment Correction and -92.4dBm Sensitivity for 802.11ba., , , , , , , and . VLSI Circuits, page 80-. IEEE, (2019)An MC-SS Platform for Short-Range Communications in the Personal Network Context., , , , , , , , and . EURASIP J. Wireless Comm. and Networking, (2008)An 802.11ba-Based Wake-Up Radio Receiver With Wi-Fi Transceiver Integration., , , , , , , , , and . IEEE J. Solid State Circuits, 55 (5): 1151-1164 (2020)A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference., , , , , and . IEEE J. Solid State Circuits, 58 (4): 1037-1050 (2023)An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET., , , , and . IEEE J. Solid State Circuits, 58 (10): 2826-2838 (October 2023)A Vector Processor for Mean Field Bayesian Channel Estimation., , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (7): 1348-1359 (2021)Adaptive and multi-mode baseband systems for next generation wireless communication., , , , , , , and . ACSSC, page 1499-1503. IEEE, (2017)