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Parameter reduction for variability analysis by slice inverse regression method.

, , , and . IET Circuits Devices Syst., 2 (1): 16-22 (2008)

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Delay Uncertainty Reduction by Interconnect and Gate Splitting., , , and . ASP-DAC, page 690-695. IEEE Computer Society, (2007)Principle Hessian direction based parameter reduction with process variation., , , and . ICCAD, page 632-637. IEEE Computer Society, (2007)Principle Hessian Direction-Based Parameter Reduction for Interconnect Networks With Process Variation., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (9): 1337-1347 (2010)Principle hessian direction based parameter reduction for interconnect networks with process variation., , , and . SLIP, page 41-46. ACM, (2007)Parameter reduction for variability analysis by slice inverse regression method., , , and . IET Circuits Devices Syst., 2 (1): 16-22 (2008)Finite-Point Gate Model for Fast Timing and Power Analysis., , , and . ISQED, page 657-662. IEEE Computer Society, (2008)A robust finite-point based gate model considering process variations., , , , and . ICCAD, page 692-697. IEEE Computer Society, (2007)A Linear Fractional Transform (LFT) Based Model for Interconnect Uncertainty., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (4): 1148-1160 (2009)Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method., , , and . ASP-DAC, page 468-473. IEEE Computer Society, (2007)