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A Novel Timing Estimation Method for Chirp-Based Systems.

, , , , , and . IEICE Trans. Commun., 94-B (12): 3607-3609 (2011)

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A Novel Timing Estimation Method for Chirp-Based Systems., , , , , and . IEICE Trans. Commun., 94-B (12): 3607-3609 (2011)Studying the near-room temperature insulator-to-metal switching in ultrathin VO2 films on (001) TiO2., , , and . ICEIC, page 1-4. IEEE, (2022)On-Chip Split Shared Data Bus Architecture for SoC., , , , and . CDES, page 104-108. CSREA Press, (2005)Design of an application specific instruction set processor for a universal bitstream codec., , , and . IEICE Electron. Express, 11 (24): 20141047 (2014)Fast human detection using selective block-based HOG-LBP., , , , , and . ICIP, page 601-604. IEEE, (2012)A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (11): 741-745 (2012)Binary-Truncated CDMA-Based On-Chip Network., , and . ISCAS, page 397-400. IEEE, (2007)A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS., , , , and . ISOCC, page 405-407. IEEE, (2011)Energy-Aware 32bit Parallel Processing Unit with Multi Operation Modes and 2 Step Data Gating Technique for Multimedia Processor., , , , and . CDES, page 80-84. CSREA Press, (2009)Level Shifter Circuit Having Dual Outputs for FPD Gate Driver., , , , , , and . VLSI, page 173-177. CSREA Press, (2003)