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REMAP+: An Efficient Banking Architecture for Multiple Writes of Algorithmic Memory.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (3): 660-671 (2020)

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Supporting compressed-sparse activations and weights on SIMD-like accelerator for sparse convolutional neural networks., and . ASP-DAC, page 105-110. IEEE, (2018)A Two-Directional BigData Sorting Architecture on FPGAs., , , and . IEEE Comput. Archit. Lett., 19 (1): 72-75 (2020)GRONA : A Framework for Gather-and-Reduce On Near-Memory Accelerators., , , , and . MCSoC, page 225-232. IEEE, (2023)Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs., , , , , , , , and . FPL, page 294-298. IEEE, (2023)On Reconfiguring Memory-Centric AI Edge Devices for CIM., , , , , , , , and . ISOCC, page 262-263. IEEE, (2021)DLPrPPG: Development and Design of Deep Learning Platform for Remote Photoplethysmography., , , and . ISCAS, page 697-701. IEEE, (2022)MSIM: A Highly Parallel Near-Memory Accelerator for MinHash Sketch., , and . SOCC, page 1-6. IEEE, (2022)Reducing radio energy consumption of key management protocols for wireless sensor networks., , , and . ISLPED, page 351-356. ACM, (2004)A Security Protocol for Biometric Smart Cards., , , and . CARDIS, USENIX, (2002)Energy-Memory-Security Tradeoffs in Distributed Sensor Networks., , and . ADHOC-NOW, volume 3158 of Lecture Notes in Computer Science, page 70-81. Springer, (2004)