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Disambiguation of "Wang, Chua-Chin"

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A Battery Interconnect Module with high voltage transceiver using 0.25 µm 60V BCD process for Battery Management Systems.

, , , and . ISOCC, page 1-4. IEEE, (2012)

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Wang- Chin Kim

Chin-hsien Wang

Stephanie Chua

Siewteen Chua

Modesto Chua

 

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One-Time-Implantable Spinal Cord Stimulation System Prototype., , , and . IEEE Trans. Biomed. Circuits Syst., 5 (5): 490-498 (2011)An SRAM design using dual threshold voltage transistors and low-power quenchers., , and . IEEE J. Solid State Circuits, 38 (10): 1712-1720 (2003)A 800 Mbps and 12.37 ps Jitter Bidirectional Mixed-Voltage I/O Buffer With Dual-Path Gate-Tracking Circuit., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (1): 116-124 (2013)A 4-kb Low-Power SRAM Design With Negative Word-Line Scheme., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 54-I (5): 1069-1076 (2007)A Self-Disabled Sensing Technique for Content-Addressable Memories., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 57-II (1): 31-35 (2010)2×VDD 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation., , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (7): 812-816 (2017)Wide-range CTAT and PTAT sensors with second-order calibration for on-chip thermal monitoring., , and . Microelectron. J., 46 (9): 819-824 (2015)An 80MHz PLL with 72.7ps peak-to-peak jitter., , , and . Microelectron. J., 38 (6-7): 716-721 (2007)Low-Power Multiplier Design Using a Bypassing Technique., and . J. Signal Process. Syst., 57 (3): 331-338 (2009)A Signed Array Multiplier with Bypassing Logic., , , and . J. Signal Process. Syst., 66 (2): 87-92 (2012)