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Automatic Generation of Instructions to Robustly Test Delay Defects in Processors.

, , , and . ETS, page 173-178. IEEE Computer Society, (2007)

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Application of Simple Genetic Algorithms to Sequential Circuit Test Generation., , , and . EDAC-ETC-EUROASIC, page 40-45. IEEE Computer Society, (1994)Single Trojan injection model generation and detection., , and . LATS, page 181. IEEE, (2016)A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware., , and . DAC, page 684-690. ACM Press, (1999)Switch-level timing simulation of bipolar ECL circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (4): 516-530 (1993)Benchmarking Parallel Processing Platforms: An Applications Perspective., , , and . IEEE Trans. Parallel Distributed Syst., 4 (8): 947-954 (1993)Complementary nano-electromechanical switches for ultra-low power embedded processors., , and . ACM Great Lakes Symposium on VLSI, page 309-314. ACM, (2009)Reducing verification overhead with RTL slicing., , , and . ACM Great Lakes Symposium on VLSI, page 399-404. ACM, (2007)Design of a scalable parallel switch-level simulator for VLSI., , and . SC, page 615-624. IEEE Computer Society, (1990)Assigning Sites fto Redundant Clusters in a Distributed Storage System., , and . ICPP (1), page 64-71. CRC Press, (1993)Fault modeling and testing of self-timed circuits., , and . VTS, page 62-66. IEEE Computer Society, (1991)