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Author's Reply.. IEEE Trans. Computers, 28 (8): 581 (1979)Test Generation for Path Delay Faults Using Binary Decision Diagrams., , and . IEEE Trans. Computers, 44 (3): 434-447 (1995)Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation., , and . ITC, page 561-565. IEEE Computer Society, (1981)Finite State Machine Synthesis with Fault Tolerant Test Function., , and . DAC, page 562-567. IEEE Computer Society Press, (1992)An efficient test data reduction technique through dynamic pattern mixing across multiple fault models., , , , and . VTS, page 285-290. IEEE Computer Society, (2011)On variable clock methods for path delay testing of sequential circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (11): 1237-1249 (1997)Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits., , , and . J. Electron. Test., 12 (3): 239-254 (1998)Editorial.. J. Electron. Test., 3 (2): 105 (1992)Editorial.. J. Electron. Test., 14 (3): 187-188 (1999)Editorial.. J. Electron. Test., 30 (6): 637-638 (2014)