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Slicing tools for synchronous reactive programs., , and . ISSTA, page 217-220. ACM, (2004)Randomized directed testing (REDIRECT) for Simulink/Stateflow models., , and . EMSOFT, page 217-226. ACM, (2008)Fully Abstract Semantics for Higher Order Communicating Systems.. MFCS, volume 629 of Lecture Notes in Computer Science, page 463-471. Springer, (1992)A formal approach to component based development of synchronous programs., , and . ASP-DAC, page 421-424. ACM, (2001)Some results on Parametric Temporal Logic., , and . Inf. Process. Lett., 111 (20): 994-998 (2011)Efficient coverage of parallel and hierarchical stateflow models for test case generation., , , and . Softw. Test. Verification Reliab., 22 (7): 457-479 (2012)Multiple Mutation Testing from Finite State Machines with Symbolic Inputs., , and . ICTSS, volume 10533 of Lecture Notes in Computer Science, page 108-125. Springer, (2017)A simulation condition for correct asynchronous implementation of synchronous design., , , and . ACC, page 1728-1733. IEEE, (2008)Extending Statecharts with Temporal Logic., and . IEEE Trans. Software Eng., 24 (3): 216-231 (1998)Model Checking of Statechart Models: Survey and Research Directions, and . ArXiv Computer Science e-prints, (July 2004)