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Disambiguation of "Philippe, Jean"

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MODÉLISATION DE LA FLEXION LIBRE D'UN CÂBLE MULTICOUCHE TENANT COMPTE DE L'ÉLASTICITÉ DES CONTACTS

. (2011)

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Jean-Philippe Dubus

Jean-Philippe Kohl

Gérard Jean-Philippe

Jean-Philippe Haumesser

Jean-Philippe Leresche

 

Other publications of authors with the same name

Design-Trotter: System-level dynamic estimation task a first step towards platform architecture selection., , , and . J. Embed. Comput., 1 (4): 565-586 (2005)A scheduling framework for system-level estimation., , and . ICECS, page 277-280. IEEE, (2000)System Level Design with UML: a Unified Approach., , , , and . IES, page 1-10. IEEE, (2006)Internet of Things: A Definition & Taxonomy., , , , and . NGMAST, page 72-77. IEEE, (2015)SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration., , , , , , , , , and 10 other author(s). CoRR, (2023)VLSI high level synthesis of fast exact least mean square algorithms based on fast FIR filters., , , and . ICASSP, page 671-674. IEEE Computer Society, (1997)Memory aspects in signal processing and HLS tool: Some results., , , and . EUSIPCO, page 1-4. IEEE, (1996)SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency., , , , , , , , , and 11 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Design-Trotter: a multimedia embedded systems design space exploration tool., , and . IEEE Workshop on Multimedia Signal Processing, page 448-451. IEEE, (2002)Estimation du parallélisme au niveau système pour l'exploration de l'espace de conception de systèmes enfouis., , , and . Technique et Science Informatiques, 22 (3): 315-349 (2003)