Author of the publication

13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 246-248. IEEE, (2024)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Hierarchical LVS Based on Hierarchy Rebuilding., and . ASP-DAC, page 379-384. IEEE, (1998)Highway Condition Analysis and Traffic Safety Monitoring System Through Analysis of Time-Series Data from LiDAR-based Probe Vehicle., , , and . SMC, page 1500-1505. IEEE, (2023)A New Hierarchical Layout Compactor Using Simplified Graph Models., , and . DAC, page 323-326. IEEE Computer Society Press, (1992)A Mobile Edge Computing Device to Support Data Collecting and Processing from IoT., , , and . ICEIC, page 1-3. IEEE, (2019)Hierarchy Restructuring for Hierarchical LVS Comparison., and . VLSI Design, 10 (1): 117-125 (1999)A staggered cell-centered DG method for the biharmonic Steklov problem on polygonal meshes: A priori and a posteriori analysis., , and . Comput. Math. Appl., (2022)13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction., , , , , , , , , and 20 other author(s). ISSCC, page 246-248. IEEE, (2024)A fully-hardwired implementation of large vocabulary continuous speech recognizer., , , and . ISCE, page 1-2. IEEE, (2015)A fast-serial finite field multiplier without increasing the number of registers., , , and . ISCAS (5), page 157-160. IEEE, (2003)Fast Prototyping of a Deep Neural Network on an FPGA., and . ISOCC, page 214-215. IEEE, (2020)