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A Thin-Film, a-IGZO, 128b SRAM and LPROM Matrix With Integrated Periphery on Flexible Foil., , , , , , , and . IEEE J. Solid State Circuits, 52 (11): 3095-3103 (2017)A low leakage 500MHz 2T embedded dynamic memory with integrated semi-transparent refresh., , and . ESSCIRC, page 523-526. IEEE, (2011)Variation-resilient sub-threshold circuit solutions for ultra-low-power Digital Signal Processors with 10MHz clock frequency., and . ESSCIRC, page 474-477. IEEE, (2012)Dense, 11 V-Tolerant, Balanced Stimulator IC with Digital Time-Domain Calibration for $100 nA Error., and . IEEE Trans. Biomed. Circuits Syst., 17 (5): 1166-1176 (October 2023)A 16nm 128kB high-density fully digital In Memory Compute macro with reverse SRAM pre-charge achieving 0.36TOPs/mm2, 256kB/mm2 and 23. 8TOPs/W., , , and . ESSCIRC, page 409-412. IEEE, (2023)Dual-Input Pseudo-CMOS Logic for Digital Applications on Flexible Substrates., , and . ESSCIRC, page 255-258. IEEE, (2021)A flexible, ultra-low power 35pJ/pulse digital back-end for a QAC UWB receiver., and . ESSCIRC, page 236-239. IEEE, (2007)A dual port dual width 90nm SRAM with guaranteed data retention at minimal standby supply voltage., and . ESSCIRC, page 290-293. IEEE, (2008)UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design., and . DATE, page 716-717. IEEE Computer Society, (2005)Embedded HW/SW platform for on-the-fly testing of true random number generators., , , , and . DATE, page 345-350. ACM, (2015)