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Thermomigration-induced void formation in Cu-interconnects - Assessment of main physical parameters., , , , , , , и . IRPS, стр. 1-7. IEEE, (2023)Assessment of critical Co electromigration parameters., , , , , , , , и . IRPS, стр. 8. IEEE, (2022)Reliability of a DME Ru Semidamascene scheme with 16 nm wide Airgaps., , , , , , , , и . IRPS, стр. 1-6. IEEE, (2021)Influence of test structure design on stress-induced-voiding using an experimentally validated Finite Element Modeling approach., , , и . Microelectron. Reliab., 51 (9-11): 1578-1581 (2011)Enhanced Cu pillar design to reduce thermomechanical stress induced during flip chip assembly., , , и . Microelectron. Reliab., (2018)Stress mitigation of 3D-stacking/packaging induced stresses., , , , , , , , и . IRPS, стр. 4. IEEE, (2018)Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs)., , , , , , , , , и 6 other автор(ы). IRPS, стр. 1-7. IEEE, (2023)Towards accurate temperature prediction in BEOL for reliability assessment (Invited)., , , , , , , , , и 1 other автор(ы). IRPS, стр. 1-7. IEEE, (2023)