( en | de | ru )

 

Disambiguation of "De, Vivek"

Author of the publication

copydeleteadd this publication to your clipboard
Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS.

, , , , , , , , and . CICC, page 1-4. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Nagarajavel Vivekananthan

Vivek Venkataramani

Vivek Ramamurthy

Vivek Bose

Vivek Shetty

 

Other publications of authors with the same name

Energy-Efficient Computing in Nanoscale CMOS.. IEEE Des. Test, 33 (2): 68-75 (2016)Variation-tolerant circuits: circuit solutions and techniques., , and . DAC, page 762-763. ACM, (2005)Comparative Analysis of Conventional and Statistical Design Techniques., , , , , and . DAC, page 238-243. IEEE, (2007)On-Die Supply-Resonance Suppression Using Band-Limited Active Damping., , , , , , , , , and 1 other author(s). ISSCC, page 286-603. IEEE, (2007)Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO., , , , , , and . IEEE J. Solid State Circuits, 55 (2): 478-493 (2020)A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS., , , , , , and . IEEE J. Solid State Circuits, 49 (4): 917-927 (2014)A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS., , , , , and . IEEE J. Solid State Circuits, 59 (1): 79-89 (January 2024)A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 50 (1): 59-67 (2015)A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 54 (12): 3316-3325 (2019)Near-threshold voltage design in nanoscale CMOS.. DATE, page 612. EDA Consortium San Jose, CA, USA / ACM DL, (2013)