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High throughput hardware design for the HEVC Fractional Motion Estimation Interpolation Unit.

, , , , , and . ICECS, page 161-164. IEEE, (2013)

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Design and FPGA Prototyping of a H.264/AVC Main Profile., , , , , , , , and . J. Braz. Comput. Soc., 13 (1): 25-36 (2007)Low-energy motion estimation memory system with dynamic management., , , , , , and . J. Real Time Image Process., 18 (6): 2495-2510 (2021)Energy-aware scheme for the 3D-HEVC depth maps prediction., , , , and . J. Real Time Image Process., 13 (1): 55-69 (2017)Performance Analysis of Depth Intra-Coding in 3D-HEVC., , , and . IEEE Trans. Circuits Syst. Video Technol., 29 (8): 2509-2520 (2019)High-Throughput and Low-Power Integrated Direct/Inverse HEVC Quantization Hardware Design., , , , and . ISCAS, page 1-5. IEEE, (2018)Pipelined Entropy Coders for JPEG Compression., , and . SBCCI, page 203-208. IEEE Computer Society, (2002)A Memory Energy Consumption Analysis of Motion Estimation Algorithms using Data Reuse in Video Coding Systems., , , , , and . SBCCI, page 31:1-31:6. ACM, (2014)Low-power and high-throughput hardware design for the 3D-HEVC depth intra skip., , , , , , , and . ISCAS, page 1-4. IEEE, (2017)Complexity control of high efficiency video encoders for power-constrained devices., , , and . IEEE Trans. Consumer Electron., 57 (4): 1866-1874 (2011)A High-Throughput Hardware Architecture for AV1 Non-Directional Intra Modes., , , , , and . IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 67-I (5): 1481-1494 (2020)