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Optimized buffer protection for network-on-chip based on Error Correction Code., , , , and . Microelectron. J., (2020)A Triple Burst Error Correction Based on Region Selection Code., , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (8): 1214-1222 (August 2023)A reduced computational effort mode-level scheme for 3D-HEVC depth maps intra-frame prediction., , and . J. Vis. Commun. Image Represent., (2018)Parallelism exploration for 3D high-efficiency video coding depth modeling mode one., , , and . J. Real Time Image Process., 17 (4): 787-797 (2020)DFPS: a fast pattern selector for depth modeling mode 1 in three-dimensional high-efficiency video coding standard., , , and . J. Electronic Imaging, 25 (6): 63011 (2016)Impact of failures in a MPSoC with shared coprocessors to extend the RISC-V ISA., , and . LADC, page 29-34. ACM, (2022)Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique., , , , , and . DATE, page 502-507. IEEE Computer Society, (2005)A 915 MHz UHF low power RFID tag., , , , , , , and . SBCCI, page 276-281. ACM, (2007)Low-area scalable hardware architecture for DMM-1 encoder of 3D-HEVC video coding standard., , , and . SBCCI, page 36-40. ACM, (2017)Fast 3D-Hevc Depth Maps Intra-Frame Prediction Using Data Mining., , , and . ICASSP, page 1738-1742. IEEE, (2018)