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A real-time 1080p 2D-to-3D video conversion system.

, , , and . IEEE Trans. Consumer Electronics, 57 (2): 915-922 (2011)

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Fast disparity estimation algorithm for mesh-based stereo image/video compression with two-stage hybrid approach., , , , and . VCIP, volume 5150 of Proceedings of SPIE, page 1521-1530. SPIE, (2003)Architecture design of stereo matching using belief propagation., , , , and . ISCAS, page 4109-4112. IEEE, (2010)Sub-microwatt correlation integral processor for implantable closed-loop epileptic neuromodulator., , , and . ISCAS, page 2083-2086. IEEE, (2010)Hardware architecture design for H.264/AVC intra frame coder., , , and . ISCAS (2), page 269-272. IEEE, (2004)Frame-level data reuse for motion-compensated temporal filtering., , , and . ISCAS, IEEE, (2006)High Throughput CORDIC-Based Systolic Array Design for the Discrete Cosine Transform., , , and . ISCAS, page 85-88. IEEE, (1994)Video Compression., and . Handbook of Signal Processing Systems, Springer, (2010)Scalable module-based architecture for MPEG-4 BMA motion estimation., , , and . ISCAS (2), page 245-248. IEEE, (2001)128-channel Spike Sorting Processor with a Parallel-folding Structure in 90nm Process., , and . ISCAS, page 1253-1256. IEEE, (2009)A hardware accelerator for video segmentation using programmable morphology PE array., , and . ISCAS (4), page 341-344. IEEE, (2002)