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A Multi-Modal Face Recognition Method Using Complete Local Derivative Patterns and Depth Maps.

, , , , and . Sensors, 14 (10): 19561-19581 (2014)

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Affine transformations for communication and reconfiguration optimization of loops on CGRAs., , , and . ISCAS, page 2541-2544. IEEE, (2013)Memory fartitioning-based modulo scheduling for high-level synthesis., , , , , and . ISCAS, page 1-4. IEEE, (2017)A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (9): 1771-1784 (2019)Efficient Scheduling of Irregular Network Structures on CNN Accelerators., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (11): 3408-3419 (2020)A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration., , , , and . IEEE Comput. Archit. Lett., 15 (2): 69-72 (2016)A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection., , , , and . IEEE J. Solid State Circuits, 55 (2): 505-519 (2020)Trainer: An Energy-Efficient Edge-Device Training Processor Supporting Dynamic Weight Pruning., , , , , , , , and . IEEE J. Solid State Circuits, 57 (10): 3164-3178 (2022)A 12.1 TOPS/W Quantized Network Acceleration Processor With Effective-Weight-Based Convolution and Error-Compensation-Based Prediction., , , , , , , and . IEEE J. Solid State Circuits, 57 (5): 1542-1557 (2022)Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays., , , and . DAC, page 64:1-64:6. ACM, (2016)LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA., , , , , and . DAC, page 16:1-16:6. ACM, (2018)