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An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements.

, , , , , , и . EWDTS, стр. 1-6. IEEE, (2019)

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Kambiz Navabi

Foroogh Navabi-Kermani

 

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SCOAP-based Directed Random Test Generation for Combinational Circuits., , , и . EWDTS, стр. 1-5. IEEE, (2019)An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements., , , , , , и . EWDTS, стр. 1-6. IEEE, (2019)Back-annotation of gate-level power properties into system level descriptions., и . NEWCAS, стр. 237-240. IEEE, (2014)A high-level language for design and modeling of hardware.. J. Syst. Softw., 18 (1): 5-18 (1992)DCim++: a C++ library for object oriented hardware design and distributed simulation., , , , , и . ISCAS, IEEE, (2006)An efficient BIST method for testing of embedded SRAMs., , и . ISCAS (5), стр. 73-76. IEEE, (2001)Programmable Routing Tables for Degradable Torus-Based Networks on Chips., , и . ISCAS, стр. 1065-1068. IEEE, (2007)Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models., , , и . CHDL, том A-32 из IFIP Transactions, стр. 569-586. North-Holland, (1993)Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment., , и . Embedded Systems and Applications, стр. 139-143. CSREA Press, (2003)A Low Power BIST Architecture for FPGA Look-Up Table Testing., и . VLSI-SOC, стр. 394-397. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)