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SCOAP-based Directed Random Test Generation for Combinational Circuits., , , и . EWDTS, стр. 1-5. IEEE, (2019)An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements., , , , , , и . EWDTS, стр. 1-6. IEEE, (2019)Back-annotation of gate-level power properties into system level descriptions., и . NEWCAS, стр. 237-240. IEEE, (2014)On-Chip Verification of NoCs Using Assertion Processors., , , , и . DSD, стр. 535-538. IEEE Computer Society, (2007)An off-line MDSI interconnect BIST incorporated in BS 1149.1., , , и . ETS, стр. 1-2. IEEE, (2014)Near-Optimal Node Selection Procedure for Aging Monitor Placement., , и . IOLTS, стр. 6-11. IEEE, (2018)A high-level language for design and modeling of hardware.. J. Syst. Softw., 18 (1): 5-18 (1992)Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models., , , и . CHDL, том A-32 из IFIP Transactions, стр. 569-586. North-Holland, (1993)Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment., , и . Embedded Systems and Applications, стр. 139-143. CSREA Press, (2003)A Low Power BIST Architecture for FPGA Look-Up Table Testing., и . VLSI-SOC, стр. 394-397. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)