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A Network Based Functional Verification Method of IEEE 1394a PHY Core.

, , , , and . ISVLSI, page 245-250. IEEE Computer Society, (2008)

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Operation scheduling for FPGA-based reconfigurable computers., , and . FPL, page 481-484. IEEE, (2009)Size aware placement for island style FPGAs., , , , and . FPT, page 28-35. IEEE, (2014)A Network Based Functional Verification Method of IEEE 1394a PHY Core., , , , and . ISVLSI, page 245-250. IEEE Computer Society, (2008)A Model for Matrix Multiplication Performance on FPGAs., , and . FPL, page 305-310. IEEE Computer Society, (2011)Sparse Tucker Tensor Decomposition on a Hybrid FPGA-CPU Platform., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (9): 1864-1873 (2021)A Model for Peak Matrix Performance on FPGAs., , and . FCCM, page 251. IEEE Computer Society, (2011)Design space exploration for sparse matrix-matrix multiplication on FPGAs., , and . I. J. Circuit Theory and Applications, 41 (2): 205-219 (2013)Energy-efficient dataflow computations on FPGAs using application-specific coarse-grain architecture synthesis., and . SIGARCH Comput. Archit. News, 40 (5): 58-63 (2012)FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels., , , , and . SIGARCH Comput. Archit. News, 44 (4): 92-97 (2016)A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (8): 1297-1308 (2016)