Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Optimizing Network Traffic for Spiking Neural Network Simulations on Densely Interconnected Many-Core Neuromorphic Platforms., , , and . IEEE Trans. Emerg. Top. Comput., 6 (3): 317-329 (2018)Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms: Problem Formulation and Performance Analysis., , , and . VLSI-SoC (Selected Papers), volume 561 of IFIP Advances in Information and Communication Technology, page 167-186. Springer, (2018)Making the Most of Scarce Input Data in Deep Learning-Based Source Code Classification for Heterogeneous Device Mapping., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (6): 1636-1648 (2022)Top-Down Profiling of Application Specific Many-core Neuromorphic Platforms., , and . MCSoC, page 127-134. IEEE Computer Society, (2015)Impact of graph partitioning on SNN placement for a multi-core neuromorphic architecture: work-in-progress., , , and . CASES, page 4:1-4:2. ACM, (2018)Toolchain integration of runtime variability and aging awareness in multicore platforms., , , and . FDL, page 1-8. IEEE, (2016)Directly-trained Spiking Neural Networks for Deep Reinforcement Learning: Energy efficient implementation of event-based obstacle avoidance on a neuromorphic accelerator., , , , , and . Neurocomputing, (December 2023)RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project., , , , , , , , , and 13 other author(s). SAMOS, volume 14385 of Lecture Notes in Computer Science, page 363-378. Springer, (2023)Monte Cimone: Paving the Road for the First Generation of RISC-V High-Performance Computers., , , , , , , , , and 2 other author(s). SOCC, page 1-6. IEEE, (2022)Flexible On-Line Reconfiguration of Multi-Core Neuromorphic Platforms., , , , , and . IEEE Trans. Emerg. Top. Comput., 9 (2): 915-927 (2021)