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Negative thinking by incremental problem solving: application to unate covering.

, , , , and . ICCAD, page 91-98. IEEE Computer Society / ACM, (1997)

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VIS: A System for Verification and Synthesis., , , , , , , , , and 6 other author(s). CAV, volume 1102 of Lecture Notes in Computer Science, page 428-432. Springer, (1996)Timed Boolean functions - a unified formalism for exact timing analysis., and . The Kluwer international series in engineering and computer science Kluwer, (1994)Integration of retiming with architectural floorplanning., , , and . Integr., 29 (1): 25-43 (2000)ESPRESSO-SIGNATURE: a new exact minimizer for logic functions., , , and . IEEE Trans. Very Large Scale Integr. Syst., 1 (4): 432-440 (1993)An Environment for Formal Verification Based on Symbolic Computations., and . Formal Methods Syst. Des., 6 (2): 191-216 (1995)DAG-aware AIG rewriting a fresh look at combinational logic synthesis., , and . DAC, page 532-535. ACM, (2006)River PLAs: a regular circuit structure., and . DAC, page 201-206. ACM, (2002)Generalized cofactoring for logic function evaluation., , and . DAC, page 155-158. ACM, (2003)Semi-detailed bus routing with variation reduction., and . ISPD, page 143-150. ACM, (2007)Scalable don't-care-based logic optimization and resynthesis., , , and . FPGA, page 151-160. ACM, (2009)