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Algorithms for Reconfiguring NoC-Based Fault-Tolerant Multiprocessor Arrays.

, , , and . Journal of Circuits, Systems, and Computers, 28 (7): 1950111:1-1950111:24 (2019)

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Compiler-assisted technique for rapid performance estimation of FPGA-based processors., , and . SoCC, page 341-346. IEEE, (2011)Fuzzy-ART based image compression for hardware implementation., , , and . APCCAS (2), page 147-150. IEEE, (2002)Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs., , and . IEEE Trans. Computers, 60 (5): 680-692 (2011)The Art of Guessing in Combined Side-Channel Collision Attacks., , and . IACR Cryptology ePrint Archive, (2019)Dynamic skewed tree for fast memory integrity verification., , and . DATE, page 642-647. IEEE, (2018)Lowering dynamic power in stream-based harris corner detection architecture., , and . FPT, page 176-182. IEEE, (2017)SNR-Centric Power Trace Extractors for Side-Channel Attacks., , , , , and . IACR Cryptology ePrint Archive, (2019)Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration., , and . ReCoSoC, page 1-8. IEEE, (2012)Rapid design of area-efficient custom instructions for reconfigurable embedded processing., and . J. Syst. Archit., 55 (1): 1-14 (2009)Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC Design., , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (3): 445-456 (2018)