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A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O.

S. Chen, M. You, Y. Yang, Y. Jin, Z. Lin, Y. Li, L. Li, G. Li, Y. Xie, Z. Zhang, B. Wang, N. Tang, F. Liu, Z. Fang, J. Liu, N. Wu, Y. Chen, L. Liu, N. Zhu, M. Li, and N. Qi. IEEE Trans. Circuits Syst. I Regul. Pap., 70 (11): 4271-4282 (November 2023)

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Li Li

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A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR.Q. Liao, Y. Zhang, S. Ma, L. Wang, L. Li, G. Li, Z. Zhang, J. Liu, N. Wu, L. Liu and 3 other author(s). IEEE J. Solid State Circuits, 57 (3): 767-780 (2022)A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O.Y. Yang, M. Zhong, Q. Ma, Z. Lin, L. Li, G. Li, L. Liu, J. Liu, N. Wu, H. Jia and 2 other author(s). ICTA, page 1-2. IEEE, (2022)A 400-Gb/s 64-QAM Optical Receiver with Monolithically Integrated TIA and Balanced-PD in 45-nm SOI CMOS.Y. Xiong, Y. Yang, Q. Ma, Y. Ren, L. Li, G. Li, J. Liu, Y. Li, B. Wang, N. Qi and 1 other author(s). ICTA, page 186-187. IEEE, (2023)A $4 112-Gb/s$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged Optics.H. Liu, N. Qi, D. Lu, Z. Dong, Z. Zhang, J. He, G. Li, L. Li, Y. Liu, Z. Dang and 6 other author(s). A-SSCC, page 1-3. IEEE, (2023)Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects.J. He, D. Lu, H. Xue, S. Chen, H. Liu, L. Li, G. Li, Z. Zhang, J. Liu, L. Liu and 6 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 69 (11): 4345-4357 (2022)A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS.Y. Li, S. Chen, Y. Yang, Q. Ma, M. Zhong, Z. Lin, L. Li, G. Li, Z. Zhang, L. Liu and 5 other author(s). APCCAS, page 360-363. IEEE, (2022)A 224-Gb/s Inverter-Based TIA with Interleaved Active-Feedback and Distributed Peaking in 28-nm CMOS for Silicon Photonic Receivers.S. Chen, J. Xue, L. Li, G. Li, Z. Zhang, J. Liu, L. Liu, B. Wang, Y. Li, and N. Qi. ICTA, page 198-199. IEEE, (2022)A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O.S. Chen, M. You, Y. Yang, Y. Jin, Z. Lin, Y. Li, L. Li, G. Li, Y. Xie, Z. Zhang and 11 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 70 (11): 4271-4282 (November 2023)A 28GBaud High-Swing Linear Mach-Zehnder Modulators Driver for PAM-4 and Coherent Optical Communications.K. Hao, J. He, L. Li, S. Yu, L. Liu, J. Liu, N. Yu, N. Wu, and N. Qi. ICTA, page 94-95. IEEE, (2020)

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Disambiguation of "Li, Leliang"

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A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O.

Please choose a person to relate this publication to

Li Li

Li Li

Li Li

Li Li

Li Li

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Li, Leliang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O.

Please choose a person to relate this publication to

Li Li

Li Li

Li Li

Li Li

Li Li

Other publications of authors with the same name

Disambiguation

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URL
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A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O.