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Machine learning for IC design and technology co-optimization in extreme scaling.. VLSI-DAT, page 1. IEEE, (2018)Global Routing., and . Encyclopedia of Algorithms, (2016)A High-Performance Triple Patterning Layout Decomposer with Balanced Density., , , , , and . CoRR, (2014)EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation., , , and . CoRR, (2014)On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes., , , , and . IEEE Trans. Inf. Forensics Secur., 14 (2): 347-359 (2019)Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks., , , , , , and . IEEE Access, (2020)Skew Management of NBTI Impacted Gated Clock Trees., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (6): 918-927 (2013)Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (2): 185-196 (2010)Redundant Local-Loop Insertion for Unidirectional Routing., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (7): 1113-1125 (2017)Semisupervised Hotspot Detection With Self-Paced Multitask Learning., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (7): 1511-1523 (2020)