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Disambiguation of "Ampadu, Paul"

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On Hamming Product Codes With Type-II Hybrid ARQ for On-Chip Interconnects.

, and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 2042-2054 (2009)

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Erich Paulke

Barbara Paulick

Heinz-Josef Paul

Maja Pauli

Irmgard Paulus

 

Other publications of authors with the same name

A Dual-Layer Method for Transient and Permanent Error Co-Management in NoC Links., and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (1): 36-40 (2011)On Hamming Product Codes With Type-II Hybrid ARQ for On-Chip Interconnects., and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 2042-2054 (2009)Fault Intensity Map Analysis with Neural Network Key Distinguisher., , and . ASHES@CCS, page 33-42. ACM, (2019)Transient error management for partially adaptive router in network-on-chip (NoC)., and . ISCAS, page 1672-1675. IEEE, (2012)A multi-wire error correction scheme for reliable and energy efficient SOC links using hamming product codes., and . SoCC, page 59-62. IEEE, (2008)Thermal-Aware Adaptive Fault-Tolerant Routing for Hybrid Photonic-Electronic NoC., and . NoCArc@MICRO, page 33-38. ACM, (2016)FIMA: Fault Intensity Map Analysis., , and . COSADE, volume 11421 of Lecture Notes in Computer Science, page 63-79. Springer, (2019)Energy-efficient and high-performance NoC architecture and mapping solution for deep neural networks., and . NOCS, page 12:1-12:8. ACM, (2019)Breaking the energy barrier in fault-tolerant caches for multicore systems., , and . DATE, page 731-736. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Reliable ultra-low voltage cache with variation-tolerance., , and . MWSCAS, page 121-124. IEEE, (2013)