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Performance modeling for interconnects for conventional and emerging switches.

, , and . SLIP, page 1-9. IEEE Computer Society, (2013)

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Performance modeling for interconnects for conventional and emerging switches., , and . SLIP, page 1-9. IEEE Computer Society, (2013)Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node., , , , and . ISQED, page 599-603. IEEE, (2015)Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices., and . ISQED, page 203-209. IEEE, (2013)3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation., , , , , , , and . CICC, page 663-670. IEEE, (2008)Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis., , and . IEEE Open J. Comput. Soc., (2023)Beyond Motivation and Memorization: Fostering Scientific Inquiry with Games., , , and . CHI PLAY (Companion), page 323-331. ACM, (2019)Nanoelectronics in retrospect, prospect and principle., , , and . ISSCC, page 31-35. IEEE, (2010)An analytical approach to system-level variation analysis and optimization for multi-core processor., , and . ISQED, page 99-106. IEEE, (2014)Wiring resource minimization for physically-complex Network-on-Chip architectures., and . SoCC, page 261-266. IEEE, (2014)Chip-level and Input/Output Interconnects for Gigascale SOCs: Limits and Opportunities., and . SoCC, page 323-324. IEEE, (2006)