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A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications.

, , , , , , , , , и . ISSCC, стр. 222-223. IEEE, (2012)

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A scalable architecture for multi-class visual object detection., , , , и . FPL, стр. 1-8. IEEE, (2015)The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism)., , , , , и . Parallel Comput., 31 (3-4): 352-370 (2005)Implementation of ISIS-SimpleScalar., , , и . PDPTA, стр. 117-123. CSREA Press, (2005)Visconti2 - a heterogeneous multi-core SoC for image-recognition applications., , , , , и . Hot Chips Symposium, стр. 1-22. IEEE, (2012)A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNs., , , , и . ISVLSI, стр. 22-27. IEEE Computer Society, (2018)A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications., , , , , , , , , и . ISSCC, стр. 222-223. IEEE, (2012)Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism., , , , , и . PDPTA, стр. 1148-1154. CSREA Press, (2003)Visual co-occurrence network: using context for large-scale object recognition in retail., , , , , , и . ESTIMedia, стр. 1-10. IEEE, (2015)A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications., , , , , , , , , и 9 other автор(ы). IEEE J. Solid State Circuits, 55 (1): 120-132 (2020)A 20.5TOPS and 217.3GOPS/mm2 Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 132-134. IEEE, (2019)