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A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications.

Y. Tanabe, M. Sumiyoshi, M. Nishiyama, I. Yamazaki, S. Fujii, K. Kimura, T. Aoyama, M. Banno, H. Hayashi, and T. Miyamori. ISSCC, page 222-223. IEEE, (2012)

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A scalable architecture for multi-class visual object detection.S. Advani, Y. Tanabe, K. Irick, J. Sampson, and V. Narayanan. FPL, page 1-8. IEEE, (2015)The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism).T. Midorikawa, D. Shiraishi, M. Shigeno, Y. Tanabe, T. Hanawa, and H. Amano. Parallel Comput., 31 (3-4): 352-370 (2005)Implementation of ISIS-SimpleScalar.T. Hanawa, T. Minai, Y. Tanabe, and H. Amano. PDPTA, page 117-123. CSREA Press, (2005)Visconti2 - a heterogeneous multi-core SoC for image-recognition applications.M. Uchiyama, H. Arakida, Y. Tanabe, T. Ike, T. Tamai, and M. Banno. Hot Chips Symposium, page 1-22. IEEE, (2012)A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNs.J. Choi, S. Srinivasa, Y. Tanabe, J. Sampson, and V. Narayanan. ISVLSI, page 22-27. IEEE Computer Society, (2018)Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism.Y. Tanabe, T. Midorikawa, D. Shiraishi, M. Shigeno, T. Hanawa, and H. Amano. PDPTA, page 1148-1154. CSREA Press, (2003)A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications.Y. Tanabe, M. Sumiyoshi, M. Nishiyama, I. Yamazaki, S. Fujii, K. Kimura, T. Aoyama, M. Banno, H. Hayashi, and T. Miyamori. ISSCC, page 222-223. IEEE, (2012)Visual co-occurrence network: using context for large-scale object recognition in retail.S. Advani, B. Smith, Y. Tanabe, K. Irick, M. Cotter, J. Sampson, and V. Narayanan. ESTIMedia, page 1-10. IEEE, (2015)A 20.5TOPS and 217.3GOPS/mm2 Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications.Y. Yamada, T. Sano, Y. Tanabe, Y. Ishigaki, S. Hosoda, F. Hyuga, A. Moriya, R. Hada, A. Masuda, M. Uchiyama and 7 other author(s). ISSCC, page 132-134. IEEE, (2019)A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications.Y. Yamada, M. Uchiyama, M. Jobashi, T. Koizumi, T. Tamai, N. Sato, J. Tanabe, K. Kimura, Y. Ojima, R. Murakami and 9 other author(s). IEEE J. Solid State Circuits, 55 (1): 120-132 (2020)

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Disambiguation of "Tanabe, Yasuki"

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A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications.

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Disambiguation of "Tanabe, Yasuki"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications.

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A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications.