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High-speed differential resistor ladder for A/D converters., , , , , и . ISCAS, стр. 1723-1726. IEEE, (2010)Truncated squarer with minimum mean-square error., , , , и . Microelectron. J., 45 (6): 799-804 (2014)Digital Synthesizer/Mixer With Hybrid CORDIC-Multiplier Architecture: Error Analysis and Optimization., , и . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (2): 364-373 (2009)Fixed-Width Multipliers and Multipliers-Accumulators With Min-Max Approximation Error., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (9): 2375-2388 (2013)An Efficient Digital Background Control for Hybrid Transformer-Based Receivers., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (12): 3068-3080 (2017)A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS., , , , и . IEEE J. Solid State Circuits, 45 (5): 1048-1060 (2010)A Novel Module-Sign Low-Power Implementation for the DLMS Adaptive Filter With Low Steady-State Error., , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (1): 297-308 (2022)Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements., , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (6): 2449-2462 (2022)A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme., , и . IEEE Trans. Computers, 56 (11): 1470-1483 (2007)High Speed Speculative Multipliers Based on Speculative Carry-Save Tree., , , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (12): 3426-3435 (2014)