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A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures.

F. Ferrandi, S. Curzel, L. Fiorin, D. Ielmini, C. Silvano, F. Conti, A. Burrello, F. Barchi, L. Benini, L. Lavagno, T. Urso, E. Calore, S. Schifano, C. Zambelli, M. Palesi, G. Ascia, E. Russo, N. Petra, D. Caro, G. Meo, V. Cardellini, S. Filippone, F. Presti, F. Silvestri, P. Palazzari, and S. Perri. CoRR, (2023)

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Giuseppe Olivato

Giuseppe Amato

Giuseppe Valenza

Giuseppe Bosco

Giuseppe Veltri

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A Closed Loop Control based Power Manager for WiNoC Architectures.M. Rusli, A. Mineo, M. Palesi, G. Ascia, V. Catania, and M. Marsono. MES, page 60-63. ACM, (2014)A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems.G. Ascia, V. Catania, and M. Palesi. PATMOS, volume 2799 of Lecture Notes in Computer Science, page 21-30. Springer, (2003)Approximate Wireless Networks-on-Chip.G. Ascia, V. Catania, S. Monteleone, M. Palesi, D. Patti, and J. Jose. DCIS, page 1-6. IEEE, (2018)On-Chip Communication Energy Reduction Through Reliability Aware Adaptive Voltage Swing Scaling.A. Mineo, M. Palesi, G. Ascia, P. Pande, and V. Catania. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (11): 1769-1782 (2016)Exploiting Data Resilience in Wireless Network-on-chip Architectures.G. Ascia, V. Catania, S. Monteleone, M. Palesi, D. Patti, J. Jose, and V. Salerno. ACM J. Emerg. Technol. Comput. Syst., 16 (2): 21:1-21:27 (2020)An efficient fuzzy system for traffic management in high-speed packet-switched networks.G. Ascia, V. Catania, and D. Panno. Soft Comput., 5 (4): 247-256 (2001)A VLSI fuzzy expert system for real-time traffic control in ATM networks.G. Ascia, V. Catania, G. Ficili, S. Palazzo, and D. Panno. IEEE Trans. Fuzzy Syst., 5 (1): 20-31 (1997)A fuzzy system index to preserve interpretability in deep tuning of fuzzy rule based classifiers.A. Nuovo, and G. Ascia. J. Intell. Fuzzy Syst., 25 (2): 493-504 (2013)DNN Model Compression for IoT Domain-Specific Hardware Accelerators.E. Russo, M. Palesi, S. Monteleone, D. Patti, A. Mineo, G. Ascia, and V. Catania. IEEE Internet Things J., 9 (9): 6650-6662 (2022)Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning.E. Russo, F. Blanco, M. Palesi, G. Ascia, D. Patti, and V. Catania. CoRR, (2024)

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Disambiguation of "Ascia, Giuseppe"

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A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures.

Please choose a person to relate this publication to

Giuseppe Olivato

Giuseppe Amato

Giuseppe Valenza

Giuseppe Bosco

Giuseppe Veltri

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ascia, Giuseppe"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures.

Please choose a person to relate this publication to

Giuseppe Olivato

Giuseppe Amato

Giuseppe Valenza

Giuseppe Bosco

Giuseppe Veltri

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures.