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Proteus: Exploiting precision variability in deep neural networks., , , , , , and . Parallel Comput., (2018)A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy., and . IEEE Comput. Archit. Lett., 6 (2): 33-36 (2007)Reducing Memory Latency via Read-after-Read Memory Dependence Prediction., and . IEEE Trans. Computers, 51 (3): 313-326 (2002)Behavior and Performance of Interactive Multi-Player Game Servers., , and . Clust. Comput., 6 (4): 355-366 (2003)Dynamic Stripes: Exploiting the Dynamic Precision Requirements of Activation Values in Neural Networks., , , and . CoRR, (2017)Optimizing Memory Translation Emulation in Full System Emulators., , , and . ACM Trans. Archit. Code Optim., 11 (4): 60:1-60:24 (2014)A dual grain hit-miss detector for large die-stacked DRAM caches., , , , , and . DATE, page 89-92. EDA Consortium San Jose, CA, USA / ACM DL, (2013)SPREX: A soft processor with Runahead execution., and . ReConFig, page 1-7. IEEE, (2012)Reducing OLTP instruction misses with thread migration., , , and . DaMoN, page 9-15. ACM, (2012)A physical level study and optimization of CAM-based checkpointed register alias table., , and . ISLPED, page 233-236. ACM, (2008)