Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Design of a Low-Power Complex Baseband Filter with Tunable Gain and Bandwidth in 65nm CMOS., , , , , and . ISOCC, page 109-110. IEEE, (2018)Design of a 400-MHz 1-V 1.4-mW CMOS RF receiver for MICS applications., , , and . ISOCC, page 228-229. IEEE, (2017)A 28GHz Quadrature Up-conversion Transmitter in 65nm CMOS for 5G mmWave Radio., , , , and . ISOCC, page 31-32. IEEE, (2019)A CMOS high-speed pulse swallow frequency divider for ΔΣ fractional-N PLL's., and . IEICE Electron. Express, 7 (12): 856-860 (2010)A 28-GHz Switched-Beam Antenna with Integrated Butler Matrix and Switch for 5G Applications., , and . Sensors, 21 (15): 5128 (2021)A 28 GHz 5-Bit Phase Shifter MMIC with 5.4° RMS Phase Error in GaN HEMT Process., , , and . ICEIC, page 1-4. IEEE, (2024)A 1.2 GHz Bandwidth Baseband Analog Circuit in 65nm CMOS for Millimeter-Wave Radio., , , and . ISOCC, page 301-302. IEEE, (2019)Design Considerations for Autocalibrations of Wide-Band ΔΣ Fractional-N PLL Synthesizers., and . J. Electr. Comput. Eng., (2011)A Fast and High-Precision VCO Frequency Calibration Technique for Wideband Delta Sigma Fractional-N Frequency Synthesizers., and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (7): 1573-1582 (2010)Design of a 1-V 3-mW 2.4-GHz fractional-N PLL synthesizer in 65nm CMOS., , and . ISOCC, page 230-231. IEEE, (2017)