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A high-speed and low-latency hardware implementation of RC4 cryptographic algorithm.

C. Sun, W. Liu, J. Cheng, N. Sun, Z. Peng, H. Sha, and W. Yu. Int. J. Circuit Theory Appl., 51 (12): 5980-5996 (December 2023)

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Jiafeng Zhang

Cheng-Yung Cheng

Ying Min Cheng

I-Fen Cheng

Xuerong Cheng

Other publications of authors with the same name

A low-overhead and high-reliability physical unclonable function (PUF) for cryptography.W. Liu, J. Cheng, N. Sun, H. Sha, M. Jin, H. Zhao, Z. Pan, J. Wang, S. Köse, and W. Yu. Integr., (2024)Tensor Linear Regression and Its Application to Color Face Recognition.Q. Gao, J. Cheng, D. Xie, P. Zhang, W. Xia, and Q. Wang. ICCV Workshops, page 523-531. IEEE, (2019)Multi-View Attribute Graph Convolution Networks for Clustering.J. Cheng, Q. Wang, Z. Tao, D. Xie, and Q. Gao. IJCAI, page 2973-2979. ijcai.org, (2020)Scheduled for July 2020, Yokohama, Japan, postponed due to the Corona pandemic..A high-speed and low-latency hardware implementation of RC4 cryptographic algorithm.C. Sun, W. Liu, J. Cheng, N. Sun, Z. Peng, H. Sha, and W. Yu. Int. J. Circuit Theory Appl., 51 (12): 5980-5996 (December 2023)A machine learning low-dropout regulator-assisted differential power analysis attack countermeasure with voltage scaling.J. Cheng, W. Liu, N. Sun, Z. Peng, C. Sun, C. Wang, Y. Bi, Y. Wen, H. Zhang, P. Zhang and 1 other author(s). Int. J. Circuit Theory Appl., 51 (7): 3105-3117 (July 2023)A low output ripple and high security on-chip voltage regulation based on Fourier transform.J. Cheng, W. Liu, N. Sun, Z. Peng, C. Sun, C. Wang, Y. Bi, Y. Wen, H. Zhang, P. Zhang and 1 other author(s). Int. J. Circuit Theory Appl., 51 (6): 2578-2591 (2023)A novel SM4 cryptographic architecture against higher order power analysis attacks.N. Sun, W. Liu, J. Cheng, Z. Peng, C. Wang, C. Sun, H. Sha, Z. Pan, M. Jin, H. Zhao and 7 other author(s). Int. J. Circuit Theory Appl., 52 (8): 4184-4198 (August 2024)A novel on-chip linear and switching mixed regulation against power analysis attacks.N. Sun, J. Cheng, W. Liu, Z. Peng, C. Sun, C. Wang, H. Sha, Y. Wang, and W. Yu. Integr., (November 2023)Deep Multi-View Subspace Clustering With Unified and Discriminative Learning.Q. Wang, J. Cheng, Q. Gao, G. Zhao, and L. Jiao. IEEE Trans. Multim., (2021)

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Disambiguation of "Cheng, Jiafeng"

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A high-speed and low-latency hardware implementation of RC4 cryptographic algorithm.

Please choose a person to relate this publication to

Jiafeng Zhang

Cheng-Yung Cheng

Ying Min Cheng

I-Fen Cheng

Xuerong Cheng

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Cheng, Jiafeng"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A high-speed and low-latency hardware implementation of RC4 cryptographic algorithm.

Please choose a person to relate this publication to

Jiafeng Zhang

Cheng-Yung Cheng

Ying Min Cheng

I-Fen Cheng

Xuerong Cheng

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A high-speed and low-latency hardware implementation of RC4 cryptographic algorithm.