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Disambiguation of "Calazans, Ney Laert Vilar"

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Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuits.

, , and . ICECS, page 669-672. IEEE, (2012)

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Loreto Vilar

Ignazio Vilardi

Fabio Vilardi

Sisi Alexandra Vilardi

David Vilar Torres

 

Other publications of authors with the same name

Evaluating the scalability of test buses., , , , , and . ISSoC, page 1-6. IEEE, (2013)A processor for IoT applications: An assessment of design space and trade-offs., , , , and . Microprocess. Microsystems, (2016)A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits., , , , and . ACM J. Emerg. Technol. Comput. Syst., 13 (2): 15:1-15:23 (2016)Requirements, Primitives and Models for Systems Specification., , and . SBCCI, page 323-330. IEEE Computer Society, (2002)Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits., , , , , and . VLSID, page 321-326. IEEE Computer Society, (2015)Leveraging QDI Robustness to Simplify the Design of IoT Circuits., , , , and . ISCAS, page 1-5. IEEE, (2020)Static Differential NCL Gates: Toward Low Power., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (6): 563-567 (2015)A path towards average-case silicon via asynchronous resilient bundled-data design., and . ECCTD, page 1-4. IEEE, (2015)HeMPS - a Framework for NoC-based MPSoC Generation., , , and . ISCAS, page 1345-1348. IEEE, (2009)Evaluation of Algorithms for Low Energy Mapping onto NoCs., , , and . ISCAS, page 389-392. IEEE, (2007)