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An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures.

A. Flores, J. Aragón, and M. Acacio. J. Supercomput., 45 (3): 341-364 (2008)

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Juan Antonio Garcia Aragon

Yunior Acosta Aragón

Hsiao-Mei Juan

Alexander Juan

Pere Juan i Tous

Other publications of authors with the same name

Energy-Effective Instruction Fetch Unit for Wide Issue Processors.J. Aragón, and A. Veidenbaum. Asia-Pacific Computer Systems Architecture Conference, volume 3740 of Lecture Notes in Computer Science, page 15-27. Springer, (2005)MLP-Aware Instruction Queue Resizing: The Key to Power-Efficient Performance.P. Petoumenos, G. Psychou, S. Kaxiras, J. Gonzalez, and J. Aragón. ARCS, volume 5974 of Lecture Notes in Computer Science, page 113-125. Springer, (2010)Confidence Estimation for Branch Prediction Reversal.J. Aragón, J. González, J. García, and A. González. HiPC, volume 2228 of Lecture Notes in Computer Science, page 214-223. Springer, (2001)The MosaicSim Simulator (Full Technical Report).O. Matthews, A. Manocha, D. Giri, M. Orenes-Vera, E. Tureci, T. Sorensen, T. Ham, J. Aragón, L. Carloni, and M. Martonosi. CoRR, (2020)Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network.A. Flores, J. Aragón, and M. Acacio. HiPC, volume 4873 of Lecture Notes in Computer Science, page 133-146. Springer, (2007)Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors.J. Aragón, D. Nicolaescu, A. Veidenbaum, and A. Badulescu. DATE, page 1374-1375. IEEE Computer Society, (2004)GPU-Accelerated High-Speed Eye Pupil Tracking System.J. Mompean, J. Aragón, P. Prieto, and P. Artal. SBAC-PAD, page 17-24. IEEE Computer Society, (2015)Efficient microarchitecture policies for accurately adapting to power constraints.J. Cebrian, J. Aragón, J. García, P. Petoumenos, and S. Kaxiras. IPDPS, page 1-12. IEEE, (2009)Power Token Balancing: Adapting CMPs to Power Constraints for Parallel Multithreaded Workloads.J. Cebrian, J. Aragón, and S. Kaxiras. IPDPS, page 431-442. IEEE, (2011)Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects.A. Flores, J. Aragón, and M. Acacio. PDP, page 147-154. IEEE Computer Society, (2010)

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Disambiguation of "Aragón, Juan L."

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An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures.

Please choose a person to relate this publication to

Juan Antonio Garcia Aragon

Yunior Acosta Aragón

Hsiao-Mei Juan

Alexander Juan

Pere Juan i Tous

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Aragón, Juan L."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures.

Please choose a person to relate this publication to

Juan Antonio Garcia Aragon

Yunior Acosta Aragón

Hsiao-Mei Juan

Alexander Juan

Pere Juan i Tous

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures.