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Compiler Support for Dynamic Speculative Pre-Execution.

, and . Interaction between Compilers and Computer Architectures, page 14-26. IEEE Computer Society, (2003)

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Design and Effectiveness of Small-Sized Decoupled Dispatch Queues., and . Euro-Par, volume 4128 of Lecture Notes in Computer Science, page 485-494. Springer, (2006)Parallel in-order execution architecture for low-power processor., , and . ISOCC, page 65-66. IEEE, (2017)Simultaneous thin-thread processors for low-power embedded systems., , , and . IEICE Electron. Express, 5 (19): 802-808 (2008)Reconstructing Out-of-Order Issue Queue., , , and . MICRO, page 144-161. IEEE, (2022)Check-In: In-Storage Checkpointing for Key-Value Store System Leveraging Flash-Based SSDs., , and . ISCA, page 693-706. IEEE, (2020)Virtual Thread: Maximizing Thread-Level Parallelism beyond GPU Scheduling Limit., , , , and . ISCA, page 609-621. IEEE Computer Society, (2016)MGMR: Multi-GPU Based MapReduce., , , , and . GPC, volume 7861 of Lecture Notes in Computer Science, page 433-442. Springer, (2013)Proactive Plan-Based Continuous Query Processing over Diverse SPARQL Endpoints., , , and . WI-IAT (1), page 161-164. IEEE Computer Society, (2015)FineReg: Fine-Grained Register File Management for Augmenting GPU Throughput., , , and . MICRO, page 364-376. IEEE Computer Society, (2018)Warped-compression: enabling power efficient GPUs through register compression., , , , , and . ISCA, page 502-514. ACM, (2015)